The present invention relates generally to computer graphics systems, and more particularly, to a multi-format, multi-operand pixel formatter for a graphics engine of a set-top box system.
Digital electronics and, in particular, digital video systems are becoming ubiquitous in today""s electronic world. One industry in which digital video systems continue to become more prevalent is television services. For instance, practically every television system now offers digital service, which requires a set-top box having a digital video system. In this setting, the digital video system can provide various functions relative to the digital television services, such as television programming information, games, internet browsing and other multimedia in a graphical format on a television display. A digital video system generally includes a processor, memory, a hardware graphics system for generating graphics, an application that provides system functionality including graphics creation, and an application program interface (API) for communicating between the application and graphics system. In operation, the digital video application provides a request for generation of a graphic to the graphics system API, and the graphics system API then generates register data for the graphics system using the digital video system processor.
Today""s two-dimensional graphics engine includes a pixel formatter which can extract multiple pixel operands, such as source pixel data, destination pixel data, and pattern pixel data, from separate memory buffers each having potentially different pixel formats and sizes. Once extracted, the pixel data enters a two-dimensional pipeline where multiple arithmetic and/or boolean operations can be performed upon the data before the resulting pixels are written back to memory. Prior to entering the two-dimensional pipeline, the three operands need to be aligned so that, in one embodiment, the pixel data entering the pipe corresponds to the same x,y two-dimensional location on the screen.
The present invention addresses the problem of how to manage what is an exceedingly complex number of input variables, alignments, and formats in a bounded manner within a pixel formatter of a two-dimensional graphics engine.
Alignment and formatting of the above-discussed operands is recognized herein to be exceedingly difficult when one or more of the following is true:
1. The source and destination pixel data support 1, 4, 8, 16, and 32 bit pixel sizes starting on a 1, 4, 8, 16 or 32 bit boundaries, respectively.
2. The pattern pixel data supports 1 bit or 8 bit pixel sizes starting on a 1 bit or 8 bit boundaries, respectively.
3. The source and destination pixel data are different formats, potentially starting at different bit boundaries in memory.
4. The pattern pixel data is a different format from the source and destination pixel data, with all having different starting bit addresses in memory.
Disclosed herein is a technique implementable, in one embodiment, within a pixel formatter. This technique simplifies the above-noted problem by reducing the number of boundary conditions to a more manageable number, thus making a more practical implementation possible.
Briefly summarized, the present invention comprises in one aspect a method of processing pixel data. This method includes: obtaining pixel data having a first alignment and a first format for conversion to a second alignment and a second format; pre-aligning the pixel data from the first alignment to a bit zero alignment; converting format of the pixel data from the first format to the second format; and post-aligning the pixel data in the second format from the bit zero alignment to the second alignment.
In enhanced embodiments, the pixel data includes either source pixel data or pattern pixel data retrieved from memory within a set-top box system, and the second alignment and second format are an alignment and a format of destination pixel data within the system. As a specific example, the pre-aligning can include pre-aligning the source pixel data or pattern pixel data to bit zero of a 32 bit word (i.e., assuming the system is a 32 bit system), wherein the first format is 1, 4, 8, 16 or 32 bits per pixel, and the second format is 16 or 32 bits per pixel.
Systems and computer program products corresponding to the above-summarized methods are also described and claimed herein.
To restate, presented herein is a pixel format and alignment technique which justifies the source and pattern pixel data to the destination pixel alignment. Thus, no shifting of the destination pixel data flow is required, which greatly simplifies the control logic as well as saving in the amount of shift circuitry. The approach presented is also easily scalable as well as configurable. A pixel formatter implementing this technique can support many different pixel formats and sizes. Prior to starting a two-dimensional graphics operation, a pixel formatter would be configured based on the source, destination and/or pattern pixel formats. This data is used to configure the dimensions of the input FIFOs, to initialize the data flow start-up conditions (alignments), and the data flow shift increment sizes. This is done independent from both the source and pattern data flows, since they are slaves to the destination pixel data flow.
A pixel formatter implemented as described herein is scalable because the same circuitry is easily used for the source pixel data flow as the pattern pixel data flow. This allows a capability for additional operands to be fetched and aligned from memory. The pattern pixel data flow can be a subset of the source pixel data flow as explained herein. (Basically, the palette look-up table array and logic of the source pixel data flow would not be used in the case of the pattern pixel data flow.)
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.